translation of input / output addresses to memory addresses

专利摘要:
TRANSLATION OF INPUT / OUTPUT ADDRESSES TO MEMORY ADDRESSES. An address provided in a request issued by an adapter is converted to an address directly usable for accessing system memory. The address includes a plurality of bits, wherein the plurality of bits includes a first portion of bits and a second portion of bits. The second bit portion is used for indexing one or more levels of address translation tables to perform the conversion, while the first bit portion is ignored for conversion. The first portion of bits is used to validate the address.
公开号:BR112012033815B1
申请号:R112012033815-3
申请日:2010-11-08
公开日:2020-11-03
发明作者:David Craddock；Thomas Gregg；Dan Greiner；Eric Norman Lais
申请人:International Business Machines Corporation；
IPC主号:

专利说明:

Background
[0001] The present invention relates, in general, to the translation of addresses in a computational environment and, in particular, to the translation of an input / output address into a memory address usable to access the system's memory in the environment.
[0002] System memory is accessible by reading and writing requests. These requests can come from various components of a computing environment, including central processing units, as well as adapters. Each request includes an address that must be used to access system memory. This address, however, usually does not have a one-to-one correspondence with a physical location in system memory. Therefore, address translation is performed.
[0003] Address translation is used to translate an address, which is provided in a way that is not directly usable for accessing system memory, in another form that is directly usable for accessing a physical location in system memory. For example, a virtual address included in a request provided by a central processing unit is translated into an actual or absolute address in the system's memory. As an additional example, a Peripheral Component Interconnect (PCI) address provided in an adapter request can be translated into an absolute address in system memory.
[0004] United States Publication No. 2008/0168208 Al, published on July 10, 2008, Gregg, "I / O Adapter LPAR Isolation in a Hypertransport Environment With Assigned Memory Space Indexing TV! Via Units Ids" describes a data processing system and method of isolating a plurality of I / O adapters in the system. The data processing system also comprises a processor set, a host bridge and a system bus that connects the processor set and the host bridge. Each of the I / O adapters has a respective ID and sends commands to the host bridge that includes one or more of the IDs of the I / O adapters. In the preferred embodiment, these IDs are unit IDs defined by HyperTransport, and the commands issued by the I / O Adapters include a Unit ID field that contains one or more I / O Adapter Unit IDs. Unit IDs are used to index a TVT to identify unique, independent system memory spaces.
[0005] United States Publication No. 2009/0182966 Al, published on July 16, 2009, Greiner et al., "Dynamic Address Translation with Frame Management" reveals a defined frame management function for a machine system's computer architecture. In one embodiment, a staff management instruction is obtained that identifies a first and second general record. The first general record contains a frame management field with a key field with access protection bits and a block size indication. If the block size indication indicates a large block, then an operand address for a large data block is obtained from the second general register. The large data block has a plurality of small blocks, each of which is associated with a corresponding storage key that has a plurality of storage key access protection bits. If the block size indication indicates a large block, the storage key access protection bits of each corresponding storage key of each small block within the large block are set with the access protection bits of the key field. Brief Summary
[0006] The deficiencies in the state of the art are overcome and additional advantages are provided through the provision of a computer program product to translate addresses in a computational environment. The computer program product includes a computer-readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform a method. The method includes, for example, obtaining an address from an adapter to be translated, the address comprising a plurality of bits, the plurality of bits comprising a first portion of bits and a second portion of bits; receiving an address range value that indicates a range of allowed addresses; address validation using at least the first bit portion and the received address range; and converting the address to a memory address usable for accessing the memory of the computing environment, converting bypassing the first bit portion and using the second bit portion to obtain address information from one or more levels of address translation tables for perform the conversion.
[0007] The methods and systems related to one or more aspects of the present invention are also described and claimed here.
[0008] Additional features and advantages are obtained through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail here and are considered part of the claimed invention. Brief Description of the Various Views of the Drawings
[0009] One or more aspects of the present invention are particularly highlighted and distinctly claimed as examples in the claims at the end of the specification. The foregoing and other objectives, characteristics and advantages of the invention are evident from the detailed description below, considered in conjunction with the accompanying drawings, in which: Figure 1 represents an embodiment of a computational environment to incorporate and use one or more aspects of the present invention; Figure 2 represents an embodiment of other details of the system memory and the I / O hub of Figure 1 according to an aspect of the present invention; Figure 3A represents an embodiment of an overview of the logic for registering a DMA (Direct Memory Access) address space for an adapter according to an aspect of the present invention; Figure 3B represents an embodiment of various details of registering the DMA address space for the adapter according to an aspect of the present invention; Figure 4 represents an embodiment of the logic for processing a DMA operation according to an aspect of the present invention; Figure 5A represents an example of the translation levels used when an entire address is used for indexing in address translation tables to translate the address and access the page; Figure 5B represents an example of translation levels used when a part of the address is ignored when indexing in address translation tables in accordance with an aspect of the present invention; Figure 5C represents examples of various formats compatible with CPU DAT usable according to one or more aspects of the present invention; Figure 5D represents examples of various formats for translating extended I / O addresses usable according to one or more aspects of the present invention; Figure 6A represents an embodiment of a Modify PCI Function Controls instruction used in accordance with an aspect of the present invention; Figure 6B represents an embodiment of a field used by the Modify PCI Function Controls instruction of Figure 6A according to an aspect of the present invention; Figure 6C represents an embodiment of another field used by the Modify PCI Function Controls instruction of Figure 6A in accordance with an aspect of the present invention; Figure 6D represents an embodiment of the contents of a function information block (FIB) used in accordance with an aspect of the present invention; Figure 7 represents an embodiment of an overview of the logic of the Modify PCI Function Controls instruction in accordance with an aspect of the present invention; Figure 8 represents an embodiment of the logic associated with an operation of registry I / O address translation parameters that can be specified by the Modify PCI Function Controls instruction in accordance with an aspect of the present invention; Figure 9 represents an embodiment of the logic associated with an operation of unregistered I / O address translation parameters that can be specified by the Modify PCI Function Controls instruction, in accordance with an aspect of the present invention; Figure 10 represents an embodiment of a computer program product that incorporates one or more aspects of the present invention; Figure 11 represents an embodiment of a host computer system for incorporating and using one or more aspects of the present invention; Figure 12 represents a further example of a computer system for incorporating and using one or more aspects of the present invention; Figure 13 represents a further example of a computer system comprising a computer network for incorporating and using one or more aspects of the present invention; Figure 14 represents an embodiment of various elements of a computer system to incorporate and use one or more aspects of the present invention; Figure 15A represents an embodiment of the execution unit of the computer system of Figure 14 to incorporate and use one or more aspects of the present invention; Figure 15B represents an embodiment of the branching unit of the computer system of Figure 14 to incorporate and use one or more aspects of the present invention; Figure 15C represents an embodiment of the loading / storage unit of the computer system of Figure 14 to incorporate and use one or more aspects of the present invention; and Figure 16 represents an embodiment of an emulated host computer system for incorporating and using one or more aspects of the present invention. Detailed Description
[0010] In accordance with an aspect of the present invention, an ability to translate addresses in a computational environment is provided. In one example, the addresses being translated are addresses provided by an adapter (referred to here as input / output (I / O) addresses) that must be translated into addresses usable for accessing system memory. To perform the address translation, several levels of address translation are used and the number of levels is based, for example, on a size of the memory address space assigned to the adapter, a size of one or more address translation tables. used in the translation and / or a page size (or other memory unit) to be accessed.
[0011] The address being translated includes a plurality of bits and, in one embodiment, only a part of those bits is used for indexing in address translation tables to obtain the translated address. The other bits are ignored for translation. For example, the address includes high-order bits and low-order bits (based on the size of the assigned address space). In this example, low-order bits are used for indexing in the address translation tables, including the page table, and for indexing on the page itself. High-order bits (regardless of value, that is, zero or non-zero) are ignored for translation and are not used for indexing in address translation tables. This reduces the number of levels of address translation tables used for translation. (The indication of low and high order bits is independent of how the bits are numbered.)
[0012] In one example, the translation is performed while providing adequate protection for an enterprise class server, such as a System z'6 'server. As an example, a full address (for example, the entire 64-bit address) is used to access memory; however, only a part of the address is used for translation. Another part of the address, which is ignored for translation, is used for validation (for example, a range check), along with at least a part of the address used for translation. Using only a portion of the address for translation, address translation searches are minimized. This is accomplished by performing various levels of translation based, for example, on the size of the DMA address space registered for access by the adapter, instead of the size of the address itself.
[0013] An embodiment of a computational environment to incorporate and use one or more aspects of the present invention is described with reference to Figure 1. In one example, a computational environment 100 is a System z® server provided by International Business Machines Corporation. System z® is based on z / Architecture® provided by International Business Machines Corporation. Details relating to z / Architecture® are described in an IBM® publication entitled "z / Architecture Principles of Operation", IBM Publication No. SA22-7832-07, February 2009. IBM®, System z® and z / Architecture® are registered trademarks of International Business Machines Corporation, Armonk, New York. Other names used herein may be trademarks, brand or product names of International Business Machines Corporation or other companies.
[0014] In one example, computational environment 100 includes one or more central processing units (CPUs) 102 coupled to system memory 104 (ie, main memory) via memory controller 106. To access memory from system 104, a central processing unit 102 issues a read or write request that includes an address used to access the system memory. The address included in the request is generally not directly usable for accessing system memory and therefore is translated into an address that is directly usable for accessing system memory. The address is translated using a translation mechanism (XLATE) 108. For example, the address is translated from a virtual address to a real or absolute address using, for example, dynamic address translation (DAT).
[0015] The request, including the translated address, is received by memory controller 106. In one example, memory controller 106 consists of hardware and is used to arbitrate access to system memory and to maintain memory consistency . This arbitration is performed for requests received from CPUs 102, as well as requests received from one or more adapters 110. Like central processing units, adapters issue requests to system memory 104 to gain access to system memory.
[0016] In one example, adapter 110 is a Peripheral Component Interconnect (PCI) or PCI Express (PCIe) adapter that includes one or more PCI functions. A PCI function issues a request that requires access to system memory. The request is routed to an input / output hub 112 (for example, a PCI hub) through one or more switches (for example, PCIe switches) 114. In one example, the input / output hub consists of hardware, including one or more state machines.
[0017] As used herein, the term adapter includes any type of adapter (for example, storage adapter, network adapter, processing adapter, PCI adapter, cryptographic adapter, other types of input / output adapters, etc.) . In one embodiment, an adapter includes an adapter function. However, in other embodiments, an adapter may include a plurality of functions of the adapter. One or more aspects of the present invention are applicable if an adapter includes an adapter function or a plurality of adapter functions. In addition, in the examples presented here, the adapter is used interchangeably with the function of the adapter (for example, the PCI function), unless otherwise indicated.
[0018] The input / output hub includes, for example, a root complex 116 that receives the request from a switch. The request includes an input / output address to be translated and, therefore, the root complex provides the address to an address translation and protection unit 118. This unit is, for example, a hardware unit that translates the E / address S for an address directly usable to access system memory 104, as described in further details below.
[0019] The request initiated from the adapter, including the translated address, is supplied to memory controller 106 through, for example, an I / O bus for memory 120. The memory controller performs its arbitration and forwards the request with the address translated into system memory at the appropriate time.
[0020] More details about the system memory and the input / output hub are described with reference to Figure 2. In this embodiment, the memory controller is not shown. However, the I / O hub can be attached to the system memory directly or via a memory controller. In one example, system memory 104 includes one or more address spaces 200. An address space is a particular portion of system memory that has been allocated to a particular component of the computing environment, such as a particular adapter. In one example, the address space is accessible by direct memory access (DMA) initiated by the adapter, and therefore the address space is referred to in the examples in this document as a DMA address space. However, in other examples, direct memory access is not used to access the address space.
[0021] In addition, in one example, system memory 104 includes address translation tables 202 used to translate an address from one that is not directly usable to access system memory to one that is directly usable. In one embodiment, there are one or more address translation tables assigned to a DMA address space, and such one or more address translation tables are configured based, for example, on the size of the address space to which it is assigned, the size of the address translation tables themselves and / or the size of the page (or other memory unit).
[0022] In one example, there is a hierarchy of address translation tables. For example, as shown in Figure 2, there is a first level table 202a (for example, a segment table) highlighted by an IOAT pointer 218 (described below) and a second lower level table 202b (for example, a page) pointed to by an entry 206a of the first level table. One or more bits of a received address 204 are used for indexing in table 202a to locate a particular entry 206a, which indicates a particular lower level table 202b. Then, one or more other address bits 204 are used to locate a particular entry 206b in that table. In this example, this entry provides the address used to locate the correct page, and additional bits at address 204 are used to locate a particular location 208 on the page to perform a data transfer. That is, the address at entry 206b and the selected bits of the received PCI address 204 are used to provide the address directly usable for accessing system memory. For example, the directly usable address is formed from a concatenation of high-order bits of the address at entry 206b (for example, 63:12 bits, in an example 4k page) and low-order bits selected from the PCI address received (for example, 11: 0 bits for a 4k page).
[0023] In one example, it is an operating system that assigns a DMA address space to a particular adapter. This task is accomplished through a registration process, which causes an initialization (via, for example, reliable software) of an entry in device table 210 for that adapter. The device table entry is located in a device table 211 located on I / O hub 112. For example, device table 211 is located within the translation and address protection unit of the I / O hub. In one example, the device table 210 entry includes a series of fields, such as: Format 212: this field includes a plurality of bits to indicate various information, including, for example, the address translation format (including the level ) a top level table of the address translation tables (for example, in the example above, the first level table); Page Size 213: this field indicates the size of a page (or other memory unit) to be accessed; PCI 214 base address and PCI 216 limit: these values provide a range used to define a DMA address space and verify that a received address (for example, PCI address) is valid; and IOAT (Input / Output Address Translation) Pointer 218: this field includes a pointer to the highest level of the address translation table used for the DMA address space.
[0024] In other embodiments, the DTE may include more, less or different information.
[0025] In one embodiment, the device table entry to be used in a particular translation is located using a request identifier (RID) located in a request issued by a PCI 220 function associated with an adapter (and / or a portion of the address). The applicant ID (for example, a 16-bit value that specifies, for example, a bus number, device number and function number) is included in the request, as well as the I / O address (for example, an address 64-bit PCIe) to be used to access system memory. The request, including the I / O address and RID, is provided, for example, to an addressable content memory (CAM) 230 via, for example, a switch 114, which is used to provide an index value. For example, the CAM includes multiple entries, each entry corresponding to an index in the device table. Each CAM entry includes the value of a RID. If, for example, the received RID matches the value contained in an entry in the CAM, the corresponding device table index is used to locate the device table entry. That is, the CAM output is used for indexing on device table 211 to locate the entry for device table 210. If there is no match, the received packet is discarded without access to system memory being executed. (In other embodiments, a CAM or other survey is not required and the RID is used as an index.)
[0026] Subsequently, the fields within the device table entry are used to guarantee the validity of the address and the configuration of the address translation tables. For example, the input address in the request is verified by the hardware of the I / O hub (for example, the protection and address translation unit) to ensure that it is within the limits defined by the base address PCI 214 and limit PCI 216 stored in the device table entry located using the RID of the request that provided the address. This ensures that the address is within the previously registered range and for which address translation tables are validly configured.
[0027] According to an aspect of the present invention, in one embodiment, to translate an I / O address (i.e., an address provided by an adapter or other component of an I / O subsystem) to a system memory address (that is, an address directly usable to access system memory), initially, a registration process is performed. This registration process registers a particular address space with a specific requestor, such as a specific adapter or adapter function. An example of an overview of this registration process is described with reference to Figure 3A.
[0028] Initially, an operating system that runs inside one of the central processing units coupled with the system memory determines a size and location of the address space that the adapter must access, STEP 300. In one example, the size of the space address is determined by the base PCI address and PCI limit defined by the operating system. The operating system determines the base and the limit using one or more criteria. For example, if the operating system wants PCI addresses to be mapped directly to the virtual addresses of the CPU, then the base and limit are defined in this way. In an additional example, if additional isolation between adapters and / or OS images is desired, then the addresses being used are selected to provide non-overlapping and disjoint address spaces. The location is also specified by the operating system and is based, for example, on the characteristics of the adapter.
[0029] Subsequently, one or more address translation tables are created to cover that DMA address space, STEP 302. As examples, the tables can be compatible with CPU address translation tables or a single format can be provided as which is supported by the input / output hub. In one example, creation includes building the tables and placing the appropriate addresses within the table entries. As an example, one of the translation tables is a 4k page table with 512 64-bit entries and each entry includes a 4k page address compatible with the assigned address space.
[0030] Subsequently, the DMA address space is registered for the adapter, STEP 304, as described in greater detail with reference to Figure 3B. In this example, it is assumed that there is one PCI function per adapter and therefore one applicant ID per adapter. This logic is performed, for example, by a central processing unit coupled to the system memory, responding to a request from the operating system.
[0031] Initially, in one embodiment, an available device table entry is selected, which must match the adapter's Applicant ID, STEP 310. That is, the Applicant ID will be used to locate a device table entry .
[0032] In addition, the base PCI address and the PCI limit are stored in the device table entry, STEP 312. In addition, the top level address translation table format is also stored in the device table entry (for example, format field) STEP 314, as well as the input / output address translation pointer (IOAT) used to point to the top level address translation table, STEP 316. This completes the registration process .
[0033] The response to the execution record, a DMA address space and corresponding address translation tables are ready for use, as well as a device table entry. Details regarding the processing of a request issued by an applicant, such as an adapter, to access system memory are described with reference to Figure 4. The processing described below is performed by the I / O hub. In one example, it is the address translation and protection unit that performs the logic. In one embodiment, initially, a DMA request is received at the input / output hub, STEP 400. For example, a PCI function issues a request that is forwarded to the PCI hub through, for example, a PCI switch. Using the applicant's ID in the request, the appropriate device table entry is found, STEP 402. Subsequently, it is determined whether the device table entry is valid, CONSULTATION 404. In one example, validity is determined by checking for a validity bit in the input itself. This bit is set, for example, in response to the execution of an enabling function request by the operating system. If enabled, the bit is set to, for example, one (that is, valid); otherwise, it remains at zero (that is, invalid). In an additional example, the bit can be set when the registration process is complete.
[0034] If the device table entry is invalid, an error is displayed, STEP 405. Otherwise, an additional determination is made as to whether the PCI address provided in the request is less than the base PCI address stored at the entry of the device table, SEE 406. If it is, then the address is out of a valid range and an error is given, STEP 407. However, if the PCI address is greater than or equal to the base address, then another determination is made if the PCI address is greater than the PCI limit value in the device table entry, SEE 408. If the PCI address is greater than the limit, then, again, an error is displayed once the address is out of the valid range, STEP 409. However, if the address is within a valid range, then processing continues.
[0035] In one example, the format provided in the device table entry is used to determine the PCI address bits in the address to be used for address translation, STEP 410. For example, if the format indicates that the level table top is a first level table with 4k pages, so bits 29:21 of the address are used for indexing the first level table; bits 20:12 are used for indexing the page table; and bits 11: 0 are used for indexing on the 4k page. The bits used depend on how many bits are required for indexing a page or table of a certain size. For example, for a 4k page with byte-level addressing, 12 bits are used to address 4096 bytes; and for a 4k page table with 512 entries, 8 bytes each, 9 bits are used to address 512 entries etc.
[0036] The PCI hub then searches and loads the appropriate address translation table entry, STEP 412. For example, initially, the top level translation table is located using the device table entry IOAT pointer . Then, the address bits (those after the high-order bits used for validity and non-translation, for example, bits 29:21 in the example above) are used to find the particular entry within that table.
[0037] It is then determined, based, for example, on the format provided in the device table entry, if the localized address translation entry has a correct format, CONSULT 414. For example, the format in the table entry of device is compared with a format indicated in the address translation entry. If equal, then the format in the device table entry is valid. Otherwise, an error is provided, STEP 415; otherwise, processing continues to determine whether this is the last table to be processed, SEE 416. That is, it determines whether there are any other address translation tables needed to obtain the real or absolute address or whether the table entry lowest level was found. This determination is made based on the provided format and size of the tables already processed. If not the last table, processing continues with STEP 412. Otherwise, the I / O hub continues processing to allow searching and loading or storing data at the translated address, STEP 418. In one example, the hub of I / O forwards the translated address to the memory controller, which uses the address to search and load or store data in the DMA location designated by the translated address.
[0038] As described above, according to one aspect of the present invention, the number of levels of translation and, therefore, the number of searches required to perform the translation is reduced. This is achieved, for example, by ignoring the high order bits of an address during translation and using only the low order bits to move through the translation tables, which are based, for example, on the size of the DMA address space assigned to the adapter. The use of a partial address versus the full address is shown in the following examples.
[0039] Referring initially to Figure 5A, an example is presented in which the entire address is used in address translation / memory access. With this prior technique, six levels of translation tables, including the page table, are required. The beginning of the highest level table (for example, the level 5 table in this example) is pointed to by an IOAT pointer, and bits from the PCI address are then used to locate an entry in the table. Each translation table entry points to the beginning of a lower level translation table or to a page (for example, an entry in the level 5 table points to the beginning of a level 4 table, etc.)
[0040] In this example, the DMA address space (DMAAS) is 6M in size and each table is 4k bytes with a maximum of 512 8-byte entries (except the level 5 table which has 128 entries based on the address size ). The address is, for example, 64 bits: FFFF C000 0009 C600. The beginning of the level 5 table is indicated by the IOAT pointer and bits 63:57 of the PCI address are used for indexing in the level 5 table to locate the beginning of the level 4 table; bits 56:48 of the PCI address are used for indexing in the level 4 table to locate the beginning of the level 3 table; bits 47:39 are used for indexing on the level 3 table to locate the beginning of the level 2 table; bits 38:30 are used for indexing on the level 2 table to locate the beginning of the level 1 table; bits 29:21 are used for indexing on the level 1 table to locate the beginning of the page table; bits 20:12 are used for indexing the page table to locate the beginning of the page; and bits 11: 0 are used to locate the entry on the 4k page. Thus, in this example, all address bits are used for translation / access.
[0041] This contrasts with the example in Figure 5B, where the address space is the same size (for example, 6M) and the address is the same, but the translation technique ignores some of the address bits during translation. In this example, bits 63:30 of the address are ignored for translation. The IOAT pointer points to the beginning of the level 1 table and bits 29:21 of the PCI address are used for indexing in the level 1 table to locate the beginning of the page table; bits 20:12 are used for indexing the appropriate page table to locate the beginning of the page; and bits 11: 0 are used for indexing on the 4k page.
[0042] As shown, the level 1 500 table includes three 502 entries, each providing an address for one of the three 504 page tables. The number of page tables required and therefore the number of other level tables, they depend, for example, on the size of the DMA address space, the size of the translation tables and / or the size of the pages. In this example, the DMA address space is 6M, and each page table is 4k, with up to 512 entries. Therefore, each page table can map up to 2M of memory (4k x 512 entries). Therefore, three page tables are required for the 6M address space. The level 1 table can contain three entries, one for each page table and, therefore, no more levels of address translation tables are needed in this example.
[0043] In an additional embodiment, there may be different formats of address translation tables used for address translation, and there may be variations within the formats. Thus, there are variations in the bits used to index a given table or page. Some of these examples are described with reference to Figures 5C and 5D.
[0044] For example, a format is a CPU DAT compatible format, where the translation tables are compatible with translation tables used for CPU DAT translations. There may be several formats compatible with CPU DAT, examples of which are described with reference to Figure 5C. As shown, a CPU DAT compliant format is a 4k 550 page DAT compliant format, and another is a 1M 552 page DAT compliant format, as examples. The number of bits shown is the number of address bits used for indexing on that page or table (or location of an entry on that page or table). For example, 12 bits 554 of a PCI address are used as an offset (bytes) of bytes on a 556 4k page; 8 bits 558 are used as an index in a table of page 560; 11 bits 562 are used as an index in a segment table 564 etc. Located under the designated address translation table is the maximum size of the address space supported by that address translation table. For example, page table 560 supports a 1M DMA address space; segment table 564 supports a 2G DMA address space, etc. In this figure, as well as in Figure 5D, K = kilobytes, M = megabytes, G = gigabytes, T = terabytes, P = petabytes and E = exabytes.
[0045] As illustrated, as the page size increases, the number of levels of translation tables decreases. For example, for 4k 556 page, a page table is required, but not required for 1M page. Other examples and variations are possible.
[0046] Another address translation format is an I / O extended address translation format, in which the extended address translation tables are used. Several examples of extended I / O address translation formats are represented in Figure 5D. For example, the following formats are shown: a 4k address translation table with 4k 570 pages; 1M address translation tables with 4k 572 pages; and 1M address translation tables with 1M 574 pages. As with CPU DAT compliant formats, the number of bits listed are the bits used to find an entry in the specific table. For example, at reference number 576, the 12 bits are an offset on the 4k page. Likewise, at reference number 578, the 9 bits are used for indexing on an I / O page table. This I / O page table allows for a DMA address space with a size of 2M. There are many other examples.
[0047] In a particular implementation, to perform the registration of a DMA address space for the adapter, an instruction referred to as a Modify PCI Function Controls (MPFC) instruction is used. For example, the operating system determines which address translation format it wants to use, creates the address translation tables for that format, and then issues the MPFC instruction with that format included as an instruction operand. In one example, the format and other operands of the instruction are included in a function information block (described below), which is an operand of the instruction. The function information block is then used to update the DTE and, in one embodiment, optionally, a function table entry (FTE) that includes the adapter's operational parameters.
[0048] An embodiment of the details related to this instruction and, particularly, the registration process, are described with reference to Figures 6A-9. Referring to Figure 6A, a Modify PCI Function Controls 600 instruction includes, for example, an opcode 602 indicating the Modify PCI Function Controls instruction; a first field 604 that specifies a location where various information about the function of the adapter for which the operational parameters are being established is included; and a second field 606 specifying a location from which a block of PCI function information (FIB) is searched and loaded. The content of the locations designated by Fields 1 and 2 is further described below.
[0049] In one embodiment, Field 1 designates a general record that includes various information. As shown in Figure 6B, the contents of the register include, for example, a function identifier 610 that identifies the function identifier of the adapter on behalf of which the modification instruction is being performed; an address space 612 designating an address space in the system memory associated with the adapter role designated by the role identifier; an operation control 614 that specifies the operation to be performed for the function of the adapter; and status 616 which provides status in relation to the instruction when the instruction is completed with a predefined code.
[0050] In one embodiment, the function identifier includes, for example, an enabling indicator that indicates whether the identifier is enabled, a function number that identifies an adapter function (this is a static identifier and can be used to index in a function table); and an instance number specifying the particular instance of that role identifier. A function identifier exists for each function of the adapter and is used to locate a function table (FTE) entry within the function table. Each function table entry includes operational parameters and / or other information associated with your adapter function. As an example, a role table entry includes: Instance number: this field indicates a specific instance of the adapter role identifier associated with the role table entry; Device table entry index (DTE) l ... n: There can be one or more device table indexes and each index is an index on a device table to find a device table entry (DTE). There are one or more device table entries per adapter role, and each entry includes information associated with your adapter role, including information used to process adapter role requests (for example, DMA requests, MSI requests) and information related to requests associated with the adapter function (for example, PCI instructions). Each device table entry is associated with an address space within the system memory assigned to the adapter role. An adapter role can have one or more address spaces within the system memory assigned to the adapter role.
[0051] Busy indicator: this field indicates whether the adapter function is busy; Permanent Error Status Indicator: this field indicates whether the adapter function is in a permanent error state; Recovery Started Indicator: this field indicates whether recovery has started for the adapter's function; Permission Indicator: this field indicates whether the operating system trying to control the adapter's role has the authority to do so; Activation Indicator: this field indicates whether the adapter function is enabled (for example, l = enabled, 0 = disabled); Applicant Identifier (RID): This is an adapter function identifier and includes, for example, a bus number, a device number and a function number.
[0052] In one example, this field is used for accessing a space for configuring the adapter function. (An adapter's memory can be defined as address spaces, including, for example, a configuration space, an I / O space, and / or one or more memory spaces.) In one example, the configuration space can be accessed by specifying the configuration space in an instruction issued by the operating system (or other configuration) for the function of the adapter. An offset in the configuration space and a function identifier used to locate the appropriate function table entry that includes the RID is specified in the instruction. The firmware receives the instruction and determines that it is for a configuration space. Therefore, it uses the RID to generate a request to the I / O hub, and the I / O hub creates a request to access the adapter. The location of the adapter role is based on the RID and the offset specifies an offset in the configuration space for the adapter role.
[0053] As used here, the firmware includes, for example, the processor microcode, milicode and / or macrocode. It includes, for example, the hardware level instructions and / or data structures used in the implementation of the top level machine code. In one embodiment, it includes, for example, proprietary code that is usually delivered as microcode that includes reliable software or microcode specific to the underlying hardware and controls the operating system's access to the system hardware.
[0054] The Base Address Register (BAR) (1 year): this field includes a plurality of unsigned integers, designated as BARo - BARn, which are associated with the adapter function originally specified and whose values are also stored in the registers base address associated with the adapter role. Each BAR specifies the starting address of a memory space or I / O space within the function of the adapter, and also indicates the type of address space, that is, whether it is a 64 or 32 bit memory space or an E space 32-bit / S, as examples;
[0055] In one example, it is used to access the memory space and / or I / O space of the adapter function. For example, an offset provided in an instruction to access the adapter function is added to the value in the base address register associated with the address space designated in the instruction to obtain the address to be used to access the adapter function. The address space identifier provided in the instruction identifies the address space within the function of the adapter to be accessed and the corresponding BAR to be used;
[0056] Size l .... n: this field includes a plurality of unsigned integers, designated as SIZEo-SIZEn. The value of a Size field, when different from zero, represents the size of each address space with each entry corresponding to a BAR previously described.
[0057] More details on BAR and Size are described below. 1. When a BAR is not implemented for an adapter function, the BAR field and its corresponding size field are both stored as zero. 2. When a BAR field represents an I / O address space or a 32-bit memory address space, the corresponding size field is different from zero and represents the size of the address space. 3. When a BAR field represents a 64-bit memory address space, a. The BARn field represents the least significant address bits. B. The next consecutive BARn + i field represents the most significant address bits. ç. The corresponding SIZEn field is non-zero and represents the size of the address space. d. The corresponding SIZEn + i field is not significant and is stored as zero.
[0058] Internal Routing Information: this information is used to perform private routing for the adapter. It includes, for example, node, processor chip and hub addressing information, for example.
[0059] Status indication: provides an indication, for example, of whether loading / storage operations are blocked or the adapter is in an error state, as well as other indications.
[0060] In one example, the busy indicator, the permanent error status indicator and the initiated recovery indicator are defined based on the monitoring performed by the firmware. In addition, the permission indicator is defined, for example, based on the policy; and the BAR information is based on configuration information discovered during a bus move by the processor (for example, processor firmware). Other fields can be defined based on configuration, initialization and / or events. In other embodiments, the function table entry may include more, less or different information. The information included may depend on the operations supported or enabled for the adapter function.
[0061] With reference to Figure 6C, in an example, Field 2 designates a logical address 620 of a PCI function information block (FIB), which includes information about an associated adapter function. The function information block is used to update a device table entry and / or function table entry (or other location) associated with the adapter function. The information is stored in the FIB during initialization and / or configuration of the adapter and / or in response to specific events.
[0062] More details about a function information block (FIB) are described with reference to Figure 6D. In one embodiment, a function information block 650 includes the following fields: Format 651: this field specifies the FIB format. Interception Control 652: this field is used to indicate whether the execution of a guest of specific instructions by a guest in paged mode results in interception of instructions; Error indication 654: this field includes the error status indication for direct access to memory and interruptions of the adapter. When the bit is set (for example, 1), one or more errors were detected when performing direct memory access or interrupting the adapter for the adapter function; Loading / Storage Block 656: this field indicates whether loading / storage operations are blocked; Valid PCI function 658: this field includes an activation control for the adapter function. When the bit is set (for example, 1), the adapter function is considered to be enabled for I / O operations; Registered Address Space 660: this field includes a direct control of enabling access to memory for an adapter function. When the field is configured (for example, 1), direct access to memory is enabled; Page Size 661: this field indicates the size of the page or other memory unit to be accessed by an access to DMA memory; PCI Base Address (PBA) 662: this field is a base address for an address space in the system memory assigned to the adapter function. Represents the lowest virtual address that an adapter function can use for direct memory access to the specified DMA address space; PCI Address Limit (PAL) 664: this field represents the highest virtual address that an adapter function can access within the specified DMA address space; Input / Output Address Translation Pointer (IOAT) 666: The input / output address translation pointer designates the first of all translation tables used by a PCI virtual address translation or can directly designate the absolute address of a storage frame that is the result of the translation; Interrupt Subclass (ISC) 668: this field includes the interrupt subclass used to present adapter interrupts for the adapter function; Number of Interruptions (NOI) 670: this field designates the number of distinct interrupt codes accepted for an adapter function. This field also defines the size, in bits, of the adapter interrupt bit vector designated by an adapter interrupt bit vector address and adapter interrupt bit vector offset fields; Adapter Interrupt Bit Vector Address (AIBV) 672: This field specifies an address of the adapter interrupt bit vector for the adapter function. This vector is used in interrupt processing; 674 Adapter Interrupt Bit Vector Offset: This field specifies the offset of the first bit of the adapter interrupt bit vector for the adapter function; Adapter Interrupt Summary (AISB) Bit Address 676: This field provides an address that designates the adapter interrupt summary bit, which is optionally used in interrupt processing; 678 Adapter Interrupt Summary Bit Offset: This field provides the offset in the adapter interrupt summary bit vector; Function Measurement Block Address (FMB) 680: this field provides an address of a function measurement block used to collect measurements in relation to the adapter's function; 682 Function Measurement Lock Key: this field includes an access key to access the function measurement block; 684 Summary Bit Notification Control: this field indicates whether there is a vector of summary bits being used; Instruction Authorization Token 686: this field is used to determine whether a paged storage mode guest is authorized to execute PCI instructions without host intervention; e In one example, on z / Architecture®, a paged guest is executed interpretively using the Start Interpretative Execution (SIE) instruction, at level 2 of interpretation. For example, the logical partition hypervisor (LPA) executes the SIE instruction to start the logical partition in physical and fixed memory. If z / VM® is the operating system on that logical partition, it issues the SIE instruction to run its guests' (virtual) machines on its V = V (virtual) storage. Therefore, the LPAR hypervisor uses level 1 SIE and the z / VM® hypervisor uses level 2 SIE; and Address Translation Format 687: this field indicates a selected format for translating addresses from the top level translation table to be used in the translation (for example, a higher level table indication (segment table, 3rd region etc.).
[0063] The function information block designated in the Modify PCI Function Controls instruction is used to modify a selected device table entry, function table entry and / or other firmware controls associated with the adapter function designated in the instructions. . When modifying the device table entry, the function table entry and / or other firmware controls, some services are provided for the adapter. These services include, for example, adapter outages; address translations; resetting the error state; reset of blocked loading / storage; definition of function measurement parameters; and definition of interception control.
[0064] An embodiment of the logic associated with the Modify PCI Function Controls instruction is described with reference to Figure 7. In one example, the instruction is issued by an operating system (or other configuration) and executed by the processor (for example, firmware) running the operating system. In the examples presented here, the adapter instruction and functions are based on PCI. However, in other examples, a different adapter architecture and corresponding instructions can be used.
[0065] In one example, the operating system provides the following operands to the instruction (for example, in one or more registers designated by the instructions): the PCI function identifier; the DMA address space identifier; an operation control; and an address of the function information block.
[0066] Referring to Figure 7, initially, it is determined whether the facility that allows a Modify PCI Function Controls instruction is installed, CONSULT 700. This determination is made, for example, by checking a stored indicator, for example , in a control block. If the facility is not installed, an exception condition is provided, STEP 702. Otherwise, it is determined whether the instruction was issued by a paged storage mode guest (or another guest), CONSULT 704. If so, the system host operation will emulate the operation for that guest, STEP 706.
[0067] Otherwise, it is determined whether one or more of the operands are aligned, SEE 708. For example, it is determined whether the address of the function information block is in a double word limit. In one example, this is optional. If the operands are not aligned, an exception condition is provided, STEP 710. Otherwise, it is determined whether the function information block is accessible, CONSULT 712. If not, an exception condition is provided, STEP 714. If otherwise, it is determined whether the identifier provided in the operands of the Modify PCI Function Controls instruction is enabled, CONSULT 716. In one example, this determination is made by checking an enabling indicator on the identifier. If the identifier is not enabled, then an exception condition is provided, STEP 718.
[0068] If the identifier is enabled, then the identifier is used to locate an entry in the function table, STEP 720. That is, at least a portion of the identifier is used as an index in the function table to locate the entry of the function table corresponding to the adapter function for which the operating parameters are to be set.
[0069] It is determined if the function table entry was found, CONSULTATION 722. If not, an exception condition is provided, STEP 724. Otherwise, if the configuration that issues the instruction is a guest, CONSULTATION 726, then , an exception condition (for example, interception for the host) is provided, STEP 728. This query can be ignored if the configuration is not a guest, or other authorizations can be verified, if assigned.
[0070] It is then determined whether the function is enabled, CONSULT 730. In one example, this determination is made by checking an activation indicator in the function table entry. If not enabled, an exception condition is provided, STEP 732.
[0071] If the function is enabled, then it is determined whether recovery is active, CONSULT 734. If recovery is active, as determined by a recovery indicator in the function table entry, an exception condition is provided, STEP 736. However, if recovery is not active, then an additional determination is made as to whether the function is occupied, CONSULT 738. This determination is made by checking the busy indicator at the entry of the function table. If the function is busy, then a busy condition is provided, STEP 740. With the busy condition, the instruction can be tried again, instead of aborted.
[0072] If the function is not occupied, then it is still determined whether the function information block format is valid, CONSULT 742. For example, the FIB format field is checked to determine if this format is supported by system. If it is invalid, then an exception condition is provided, STEP 744. If the function information block format is valid, then an additional determination is made as to whether the operation control specified in the operands of the instruction is valid, CONSULTATION 746. Yes, the operation control is one of the operation controls specified for this instruction. If it is invalid, then an exception condition is provided, STEP 748. However, if the operation control is valid, then processing continues with the specific operation control being specified.
[0073] An operation control that can be specified is an operation of register I / O address translation parameters used in address translation control for an adapter. With this operation, the parameters of the PCI function relevant to the translation of I / O addresses are defined in the DTE, FTE and / or elsewhere from the appropriate parameters of the FIB, which is an operand for the instruction. These parameters include, for example, the base PCI address; the PCI address limit (that is, PCI limit or limit); the address translation format; the page size; and the I / O address translation pointer, which are operands for this operation. There are also implicit operands, including a starting DMA address (SDMA) and a final DMA address (EDMA), which are stored in a location accessible to the processor that executes the instructions.
[0074] An embodiment of the logic for establishing the operational parameters for the translation of I / O addresses is described with reference to Figure 8. Initially, it is determined if the PCI base address in the FIB is greater than the PCI limit in the FIB, CONSULT 800. If the comparison of the base address and the limit indicates that the base address is greater than the limit, then an exception condition is recognized, STEP 802. However, if the base address is less than or equal to the limit, then , an additional determination will be made as to whether the address translation format and page size are valid, SEE 804. If they are invalid, then an exception condition is provided, STEP 806. However, if they are valid, then, an additional determination is made as to whether the size of the address space (based on the base address and the limit) exceeds the translation capacity, SEE 808. In one example, the size of the address space is compared to the maximum possible capacity translation translations of ende based on the format of the top level table. For example, if the top level table is a DAT compliant segment table, the maximum translation capacity is 2 Gbytes.
[0075] If the size of the address space exceeds the conversion capacity, then an exception condition is provided, STEP 810. Otherwise, an additional determination is made as to whether the base address is less than the initial DMA address, CONSULTATION 812. If positive, then an exception condition is provided, STEP 814. Otherwise, another determination is made as to whether the address limit is greater than the final DMA address, CONSULTATION 816. If positive, then a condition exception code is provided, STEP 818. In one example, the starting DMA address and the ending DMA address are based on a system policy.
[0076] Subsequently, it is determined whether sufficient resources, if necessary, are available to perform an I / O address translation, CONSULTATION 820. If negative, an exception condition, STEP 822 is provided. Otherwise, a determination is made further information on whether the I / O address translation parameters have already been registered with the FTE and DTE, CONSULTATION 824. This is determined by checking the parameter values in the FTE / DTE. For example, if the values in the FTE / DTE are zero or another defined value, then the registration has not been carried out. To locate the FTE, the identifier provided in the instruction is used and, to locate the DTE, a device index is used in the FTE.
[0077] If the adapter function has already been registered for address translation, then an exception condition is provided, STEP 826. If not, a determination is made as to whether the specified DMA address space is valid (that is, is an address space for which a DTE has been activated), CONSULTATION 828. If not, an exception condition is provided, STEP 830. If all checks are successful, then the translation parameters are placed in the table entry of the device and, optionally, in the entry of the corresponding function table (or other designated location), STEP 832. For example, the parameters of the PCI function relevant to the translation of I / O addresses are copied from the function information block and placed in the DTE / FTE. These parameters include, for example, the base PCI address, the PCI address limit, the translation format, the page size and the I / O address translation pointer. This operation allows DMA access to the specified DMA address space. It allows the translation of I / O addresses for the function of the adapter.
[0078] Another operation control that can be specified by the Modify PCI Function Controls instruction is an operation of unregistered I / O address translation parameters, an example of which is described with reference to Figure 9. With this operation, the function parameters relevant to the translation of I / O addresses are reset to zero. This operation disables DMA accesses for the specified DMA address space and purges buffer entries from the I / O translation part for that DMA address space. Disables address translation.
[0079] With reference to Figure 9, in one embodiment, it is determined whether the parameters for translating I / O addresses are not registered, CONSULT 900. In one example, this determination is made by checking the values of the appropriate parameters in the FTE or DTE. If these fields are zero or some specified value, they are not registered. Therefore, an exception condition is provided, STEP 902. If they are registered, then it is determined whether the DMA address space is valid, CONSULT 904. If it is invalid, then an exception condition is provided, STEP 906. If the DMA address space is valid, then the translation parameters in the device table entry and, optionally, in the corresponding function table entry are deleted, STEP 908.
[0080] The detailed description above is an efficient mechanism for translating an input / output address provided by an adapter to a system memory address. In one example, the full PCI address (for example, the entire 64-bit address) is used to access memory; however, address translation searches are minimized using only part of the address for translation. While using the full address provides additional protection, using, for example, only the lower-order bits for translation allows for more efficient translation through lesser levels of translation search. This allows the flexibility of the operating system to use addresses that can coexist or be the same as the virtual addresses of the operating system. In addition, it allows CPU address translation tables to be shared by adapters, allowing I / O to reduce the number of tables that need to be scanned. In addition, additional protection is provided by allowing different adapters and / or operating systems to use disjoint address space ranges.
[0081] In the embodiments described here, the adapters are PCI adapters. PCI, as used herein, refers to any adapters implemented according to a PCI-based specification, as defined by the Peripheral Components Interconnection Special Interest Group (PCI-SIG), including, without limitation, PCI or PCIe. In a specific example, Express Peripheral Component Interconnection (PCIe) is a component-level interconnection standard that defines a two-way communication protocol for transactions between I / O adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission over a PCIe bus. Transactions that originate on I / O adapters and end on host systems are referred to as bottom-up transactions. Transactions that originate on host systems and end on I / O adapters are referred to as descendant transactions. The PCIe topology is based on unidirectional point-to-point links that are paired (for example, an uplink, a downlink) to form the PCIe bus. The PCIe standard is maintained and published by PCI-SIG.
[0082] As will be appreciated by one skilled in the art, aspects of the present invention can be incorporated as a computer program system, method or product. Consequently, aspects of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining aspects of software and hardware that can generally be referred to here as a "circuit", "module" or "system". In addition, aspects of the present invention may take the form of a computer program product incorporated in one or more computer-readable media having a computer-readable program code incorporated therein.
[0083] Any combination of one or more computer-readable media can be used. The computer-readable medium may be a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, electromagnetic, infrared or semiconductor system, apparatus or device, or any suitable combination thereof. More specific examples (non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection with one or more wires, a portable floppy disk, a hard disk, a random access memory (RAM), a memory read-only (ROM), erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a read-only portable compact disc (CD-ROM) memory, an optical storage device, a storage device magnetic or any combination of these. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in connection with a system, apparatus or device for executing instructions.
[0084] Referring now to Figure 10, in one example, a computer program product 1000 includes, for example, one or more computer-readable storage media 1002 to store logic or computer-readable program code media therein. 1004 to provide and facilitate one or more aspects of the present invention.
[0085] The program code embedded in a computer-readable medium may be transmitted using an appropriate medium, including, but not limited to, wireless, cable, fiber optic cable, RF etc., or any suitable combination thereof.
[0086] The computer program code to perform operations for aspects of the present invention can be written in any combination of one or more programming languages, including an object-oriented programming language, such as Java, Smalltalk, C ++ or similar, and conventional procedural programming languages, such as the "C" programming language, assembly language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, over the Internet using an Internet service provider).
[0087] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to the embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a general purpose computer processor, special purpose computer or other programmable data processing device to produce a machine, so the instructions, which are executed through the computer's processor or other programmable data processing apparatus, create means to implement the functions / actions specified in the flowchart and / or block or blocks of the block diagram.
[0088] These computer program instructions can also be stored on a computer-readable medium that can direct a computer, other programmable data processing device or other devices to function in a particular way, so that the instructions stored in the readable medium by computer produce an article of manufacture including instructions that implement the function / action specified in the flowchart and / or blocks or block of the block diagram.
[0089] Computer program instructions can also be loaded onto a computer, other than a programmable data processing device, or other devices to cause a series of operational steps to be performed on the computer, other programmable devices or other devices to produce a computer-implemented process, such that instructions that are executed on the computer or other programmable device provide processes to implement the functions / actions specified in the flowchart and / or blocks or block of the block diagram.
[0090] The flowchart and block diagrams in the figures illustrate the architecture, functionality and operation of possible implementations of systems, methods and products of computer programs in accordance with various embodiments of the present invention. In this sense, each block in the flowchart or block diagrams can represent a module, segment or part of code, which comprises one or more executable instructions to implement the specified logical function (s). It should also be noted that, in some alternative implementations, the functions observed in the block may occur out of the order observed in the figures. For example, two blocks shown in succession can, in fact, be executed substantially at the same time, or the blocks can sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by application-based hardware-based systems that perform the functions or specified actions, or combinations of computer instructions and application-specific hardware.
[0091] In addition to the above, one or more aspects of the present invention can be provided, provided, implanted, managed, attended to etc. by a service provider that offers customer environment management. For example, the service provider can create, maintain, support, etc. computer code and / or a computer infrastructure that performs one or more aspects of the present invention for one or more customers. In return, the service provider may receive payment from the customer under a subscription and / or contract, as examples. Additionally or alternatively, the service provider may receive payment for the sale of advertising content to one or more third parties.
[0092] In one aspect of the present invention, an application can be deployed to carry out one or more aspects of the present invention. As an example, an application deployment comprises providing operable computer infrastructure to perform one or more aspects of the present invention.
[0093] As an additional aspect of the present invention, a computational infrastructure can be implemented comprising the integration of computer-readable code into a computational system, in which the code, in combination with the computational system, is capable of accomplishing one or more aspects of the present invention.
[0094] Still as an additional aspect of the present invention, a process for integrating computational infrastructure comprising integrating computer-readable code into a computer system can be provided. The computer system comprises a computer-readable medium, in which the computer medium comprises one or more aspects of the present invention. The code, in combination with the computer system, is capable of realizing one or more aspects of the present invention.
[0095] Although several embodiments are described above, they are only examples. For example, computational environments of other architectures can incorporate and use one or more aspects of the present invention. As examples, servers other than System z® servers, such as Power Systems servers or other servers provided by International Business Machines Corporation or servers of other companies, may include using and / or benefiting from one or more aspects of the present invention. In addition, although in the example presented here, adapters and the PCI hub are considered part of the server, in other embodiments, they do not necessarily have to be considered part of the server, but can simply be considered coupled to system memory and / or other components of a computational environment. The computing environment does not have to be a server. In addition, although adapters are based on PCI, one or more aspects of the present invention are usable with other adapters or other I / O components. PCI adapter and adapter are just examples. In addition, other sizes of address spaces, address tables and / or pages can be used without departing from the present invention. In addition, DTE may include more, less or different information. In addition, other types of addresses can be translated using one or more aspects of the present invention. Many other variations are possible.
[0096] In addition, other types of computing environments can benefit from one or more aspects of the present invention. As an example, a data processing system suitable for storing and / or executing program code is usable, which includes at least two processors coupled directly or indirectly to memory elements via a system bus. Memory elements include, for example, local memory used during the actual execution of the program code, mass storage and cache memory that provide temporary storage of at least some program code to reduce the number of times the code must be retrieved of mass storage during execution.
[0097] Input / output or I / O devices (including, without limitation, keyboards, screens, indicating devices, DASD, tape, CDs, DVDs, pendrives and other memory media etc.) can be coupled to the system directly or through intermediate I / O controllers. Network adapters can also be coupled to the system to allow the data processing system to be coupled with other data processing systems or remote printers or storage devices over intermediate public or private networks. Modems, cable modems and Ethernet cards are just a few of the available types of network adapters.
[0098] Referring to Figure 11, representative components of a host computer system 5000 to implement one or more embodiments are depicted. Representative host computer 5000 comprises one or more CPUs 5001 in communication with computer memory (i.e., central storage) 5002, as well as I / O interfaces for 5011 storage media devices and 5010 networks for communication with other computers or SANs and the like. The 5001 CPU is compatible with an architecture having a configured architecture instruction and architecture functionality. The 5001 CPU can have dynamic address translation (DAT) 5003 to transform program addresses (virtual addresses) into real memory addresses. A DAT typically includes a translation lookaside buffer (TLB) 5007 for temporary translations so that subsequent access to computer memory block 5002 does not require postponing the address translation. Typically, a cache memory 5009 is employed between computer memory 5002 and processor 5001. Cache memory 5009 can be hierarchical with ample cache memory available for more than one CPU, and smaller, faster (lower level) cache memories between the large cache memory and each CPU. In some implementations, the lower level cache memories are split to provide separate low level cache memories for data access and instruction search and loading. In one embodiment, an instruction is searched and loaded from memory 5002 by an instruction search unit 5004 through a cache memory 5009. The instruction is decoded into an instruction decoding unit 5006 and dispatched (with other instructions in some embodiments) for the instruction execution unit or units 5008. Typically, several execution units 5008 are employed, for example, an arithmetic execution unit, a floating point execution unit and a branch instruction execution unit. The instruction is executed by the execution unit, accessing specified instruction or memory register operands as needed. If an operand is to be accessed (loaded or stored) from memory 5002, a loading / storage unit 5005 typically manages access under the control of the instruction being executed. The instructions can be executed in hardware circuits or in internal microcode (firmware) or by a combination of both.
[0099] As noted, a computer system includes information in local (or main) storage, as well as addressing, protection, and reference and change registration. Some aspects of addressing include the address format, the concept of address spaces, the various types of addresses and the way in which one type of address is translated into another type of address. Part of the main storage includes permanently assigned storage locations. The main storage provides the system with directly addressable, fast-access data storage. Both data and programs must be loaded into main storage (from input devices) before they can be processed.
[0100] The main storage can include one or more smaller, quick access temporary memory stores, sometimes called cache memory. A cache memory is typically physically associated with a CPU or an I / O processor. The effects, except for performance, of physical construction and use of different storage media are not generally observable by the program.
[0101] Separate cache memories can be kept for instructions and data operands. The information inside a cache is kept in contiguous bytes in an integral boundary called a cache block or cache line (or line, for short). A model can provide an EXTRACT CACHE ATTRIBUTE statement that returns the size of a line of cache memory in bytes. A model can also provide PREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions that pre-fetch and load storage into the data cache or instruction or flush data from the cache memory.
[0102] Storage is viewed as a long horizontal bit chain. For most operations, access to storage proceeds in a sequence from left to right. The bit string is subdivided into units of eight bits. An eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte location in the store is identified by a unique non-negative integer, which is the address of that byte location or, simply, the byte address. Adjacent byte locations have consecutive addresses, starting with 0 on the left and proceeding in a sequence from left to right. Addresses are unsigned binary integers and are 24, 31, or 64 bits.
[0103] Information is transmitted between the storage and a CPU or a one-byte channel subsystem, or a group of bytes, at once. Unless otherwise specified, for example, in z / Architecture®, a group of bytes in storage is addressed by the leftmost byte of the group. The number of bytes in the group is implied or explicitly specified by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, for example, in z / Architecture®, the bits are numbered in a sequence from left to right. In z / Architecture®, the leftmost bits are generally referred to as the "higher order" bits and the rightmost bits as the "lower order" bits. Bit numbers are not storage addresses, however. Only bytes can be addressed. To operate on individual bits of a byte in storage, the entire byte is accessed. The bits in a byte are numbered from 0 to 7, from left to right (for example, in z / Architecture®). The bits in an address can be numbered 8-31 or 40-63 for 24-bit addresses, or 1-31 or 33-63 for 31-bit addresses; they are numbered 0-63 for 64-bit addresses. Within any other fixed-length multi-byte format, the bits making up the format are consecutively numbered starting at 0. For error detection purposes and, preferably, for correction, one or more check bits can be transmitted with each byte or with a group of bytes. Such check bits are automatically generated by the machine and cannot be directly controlled by the program. Storage capacities are expressed in number of bytes. When the length of a storage operand field is implied by the operation code of an instruction, the field is said to have a fixed length, which can be one, two, four, eight or sixteen bytes. Larger fields may be involved for some instructions. When the length of a storage operand field is not implied, but is explicitly defined, the field is said to have a variable length. Operands with variable length can vary in length in increments of one byte (or with some instructions, in multiples of two bytes or other multiples). When the information is placed in storage, the contents of only those byte locations are replaced, which are included in the designated field, although the width of the physical path for storage may be greater than the length of the field being stored.
[0104] Certain units of information must be at an integral boundary in storage. A boundary is called an integral for an information unit when its storage address is a multiple of the unit's length in bytes. Special names are given to fields of 2, 4, 8 and 16 bytes in an integral boundary. A half word is a group of two consecutive bytes in a two-byte boundary and is the basic building block of instructions. A word is a group of four consecutive bytes on a four-byte boundary. A double word is a group of eight consecutive bytes on an eight-byte border. A quadrangular word is a group of 16 consecutive bytes on a 16-byte border. When storage addresses designate half words, words, double words and square words, the binary representation of the address contains one, two, three or four rightmost zero bits, respectively. Instructions must be in integral two-byte boundaries. The storage operands of most instructions do not have border alignment requirements.
[0105] On devices that implement separate cache memories for data and instruction operands, a significant delay can be experienced if the program is stored in a cache memory line from which instructions are subsequently searched and loaded, regardless of whether the storage changes the instructions that are subsequently fetched and loaded.
[0106] In one embodiment, the invention can be practiced by software (generally referring to licensed internal code, firmware, microcode, milicode, pico-code and the like, any of which must be consistent with one or more embodiments). Referring to Figure 11, the software program code that incorporates one or more aspects can be accessed by the processor 5001 of the host system 5000 from long-term storage media devices 5011, such as a CD-ROM drive, tape drive or hard disk drive. The software program code can be implemented on any of a variety of known media for use with a data processing system, such as a floppy disk, hard disk or CD-ROM. The code can be distributed on such media or can be distributed to users from computer memory 5002 or storage from one computer system on a 5010 network to other computer systems for use by users of those other systems.
[0107] The software program code includes an operating system that controls the function and interaction of the various computer components and one or more application programs. The program code is normally paged from the storage medium device 5011 to the computer storage of relatively higher speed 5002, where it is available for processing by the 5001 processor. The techniques and methods for embedding software program code in memory , in physical media, and / or distributing software code over networks are well known and will not be discussed further in this document. Program code, when created and stored on a tangible medium (including, but not limited to, electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like) is generally referred to as a " computer program product ". The computer program product medium is typically readable by a processing circuit, preferably on a computer system for execution by the processing circuit.
[0108] Figure 12 illustrates a representative workstation or server hardware system, on which the present invention can be practiced. The 5020 system of Figure 12 comprises a representative base computer system 5021, such as a personal computer, a workstation or a server, including optional peripheral devices. The base computer system 5021 includes one or more 5026 processors and a bus employed to connect and allow communication between the 5026 processor (s) and the other components of the 5021 system according to known techniques. The bus connects processor 5026 to memory 5025 and long-term storage 5027, which can include a hard disk (including any magnetic media, CD, DVD and Flash memory, for example) or a tape drive, for example. The 5021 system must also include a user interface adapter, which connects the 5026 microprocessor, via the bus, to one or more interface devices, such as a 5024 keyboard, a 5023 mouse, a 5030 printer / scanner and / or others interface devices, which can be any user interface device, such as a touch screen, digitized input keyboard, etc. The bus also connects a 5022 display device, such as a monitor or LCD screen, to the 5026 microprocessor through a display adapter.
[0109] The 5021 system can communicate with other computers or computer networks through a network adapter capable of communicating 5028 with a 5029 network. Examples of network adapters are communication channels, token ring, Ethernet or modems. Alternatively, the 5021 system can communicate using a wireless interface, such as a CDPD card (cellular digital packet data). The 5021 system can be associated with such other computers on a Local Area Network (LAN) or a Wide Area Network (WAN), or the 5021 system can be a client in a client / server arrangement with another computer etc. All of these configurations, as well as appropriate communication hardware and software, are known in the art.
[0110] Figure 13 illustrates a 5040 data processing network, in which the present invention can be practiced. The data processing network 5040 can include a plurality of individual networks, such as a wireless network and a cable network, each of which can include a plurality of individual workstations 5041, 5042, 5043, 5044. Additionally, as will be understood by those skilled in the art, one or more LANs may be included, in which a LAN may comprise a plurality of intelligent workstations coupled to a host processor.
[0111] Still referring to Figure 13, networks can also include computers or mainframe servers, such as a gateway computer (5046 client server) or application server (remote 5048 server that can access a data store and can also be accessed directly from a 5045 workstation). A 5046 gateway computer serves as an entry point into each individual network. A gateway is required when connecting one network protocol to another. The 5046 gateway can preferably be connected to another network (the Internet 5047, for example) through a communication link. The 5046 gateway can also be directly coupled to one or more workstations 5041, 5042, 5043, 5044 using a communication link. The gateway computer can be deployed using an IBM eServer ™ System z® server provided by International Business Machines Corporation.
[0112] Referring simultaneously to Figure 12 and Figure 13, the software programming code that can incorporate the present invention can be accessed by the 5026 processor of the 5020 system from the 5027 long-term storage medium, such as a unit CD-ROM or hard disk. The software programming code can be incorporated into any of a variety of known means for use with a data processing system, such as a floppy disk, hard disk or CD-ROM. The code can be distributed in such media or it can be distributed to 5050, 5051 users from the memory or storage of a computer system on a network to other computer systems for use by users of such other systems.
[0113] Alternatively, the programming code can be incorporated into the 5025 memory and accessed by the 5026 processor using the processor bus. Such programming code includes an operating system that controls the function and interaction of the various computer components and one or more 5032 application programs. The program code is normally paged from the 5027 storage medium to the 5025 high speed memory, where it is available for processing by the 5026 processor. The techniques and methods for embedding software programming code in memory, in physical media, and / or distributing software code over networks are well known and will no longer be discussed in this document. Program code, when created and stored on a tangible medium (including, but not limited to, electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like) is generally referred to as a " computer program product ". The computer program product medium is typically readable by a processing circuit, preferably on a computer system for execution by the processing circuit.
[0114] The cache memory that is most readily available to the processor (usually faster and smaller than other processor cache memories) is the lowest cache memory (LI or level one) and the main storage (main memory) is the higher level cache memory (L3 if there are 3 levels). The lowest level cache memory is generally divided into an instruction cache memory (I-Cache) carrying machine instructions to be executed and a data cache memory (D-Cache) carrying data operands.
[0115] Referring to Figure 14, an exemplary processor embodiment is presented for the 5026 processor. Typically, one or more levels of cache memory 5053 are employed in temporary memory blocks in order to improve the performance of the processor. The 5053 cache memory is a high-speed buffer carrying lines of memory data cache that are likely to be used. Typical cache memory lines have 64, 128 or 256 bytes of memory data. Separate cache memories are generally used for cache instructions instead of cache data. Coherence of cache memory (synchronization of line copies in memory and cache memories) is generally provided by several snoop algorithms well known in the art. The main system storage 5025 of a processor system is generally referred to as a cache memory. In a processor system having 4 levels of cache memory 5053, main storage 5025 is generally referred to as level 5 (L5) cache memory as it is typically faster and only carries the portion of non-volatile storage (DASD, tape etc.) that is available to a computer system. Main storage 5025 "caches" pages of data paged in and out of main storage 5025 by the operating system.
[0116] A program counter (instruction counter) 5061 keeps track of the address of the current instruction to be executed. A program counter on a z / Architecture® processor is 64-bit and can be truncated to 31 or 24 bits to support previous addressing limits. A program counter is typically incorporated into a computer's Program Status Word (PSW), such that it persists during context switching. In this way, a program in progress, having a program counter value, can be interrupted, for example, by the operating system (switching context from the program environment to the operating system environment). The program's PSW maintains the program counter value while the program is not active, and the operating system's program counter (on the PSW) is used while the operating system is running. Typically, the program counter is incremented by an amount equal to the number of bytes in the current instruction. RISC (Reduced Instruction Set Computing) instructions are typically of fixed length while CISC (Complex Instruction Set Computing) instructions are typically of variable length. IBM z / Architecture® instructions are CISC instructions having a length of 2, 4 or 6 bytes. The program counter 5061 is modified by a context switching operation or a branch instruction branching operation, for example. In a context switching operation, the current program counter value is saved in the program status word along with other status information about the program being executed (such as condition codes), and a new program counter value is loaded by pointing to an instruction for a new program module to be executed. A branch making operation is performed to allow the program to make decisions or to allow a loop within the program by loading the result of the branch instruction into the program counter 5061.
[0117] Typically, a 5055 instruction search unit is employed to search and load instructions on behalf of the 5026 processor. The search and load unit searches and loads the 'next sequential instructions', target instructions for branch making instructions. , or the first instructions of a program after a context switch. Modern Instruction search and load units generally employ prefetch and load techniques to speculatively search and load instructions based on the likelihood that pre-fetched and loaded instructions will be used. For example, a search and load unit can search and load 16 instruction bytes that include the next sequential instruction and additional bytes of additional sequential instructions.
[0118] The searched instructions are then executed by the 5026 processor. In one embodiment, the searched instructions are passed to a 5056 sending unit of the search and loading unit. The sending unit decodes the instructions and forwards information about the decoded instructions to the appropriate 5057, 5058, 5060 units. A 5057 execution unit will typically receive information about decoded arithmetic instructions from the 5055 instruction search unit and will perform arithmetic operations on operands according to the instruction's operation code. Operands are supplied to the execution unit 5057 preferably from memory 5025, architecture records 5059 or from an immediate field of the instruction being executed. Execution results, when stored, are stored in 5025 memory, 5059 registers or other machine hardware (such as control registers, PSW registers and the like).
[0119] A 5026 processor typically has one or more units 5057, 5058, 5060 for executing the instruction function. Referring to Figure 15A, an execution unit 5057 can communicate with general architecture registers 5059, a decode / send unit 5056, a load storage unit 5060, and other 5065 processor units through 5071 interface logic. An execution unit 5057 can employ several register circuits 5067, 5068, 5069 to maintain information that the 5066 arithmetic logic unit (ALU) will operate. ALU performs arithmetic operations, such as addition, subtraction, multiplication and division, as well as a logical function, such as and, OU and OU-exclusive (XOR), rotate and swap. Preferably, the ALU supports specialized operations that are project dependent. Other circuits can provide other 5072 architecture facilities including condition codes and recovery support logic, for example. Typically, the result of an ALU operation is maintained on a 5070 checkout circuit that can route the result to a variety of other processing functions. There are several arrangements of processor units, the present description is only intended to provide a representative understanding of an embodiment.
[0120] An ADD instruction, for example, would be executed in a 5057 execution unit having arithmetic and logic functionality while a floating point instruction, for example, would be executed in a floating point execution having specialized floating point capability. Preferably, an execution unit operates on operands identified by an instruction executing a function defined by operation code in the operands. For example, an ADD instruction can be executed by a 5057 execution unit on operands found in two 5059 records identified by instruction record fields.
[0121] The execution unit 5057 performs the arithmetic addition in two operands and stores the result in a third operand, where the third operand can be a third record or one of the two source records. The execution unit preferably uses a 5066 Arithmetic Logic Unit (ALU) that is capable of performing a variety of logic functions, such as Shift, Rotate, AND, OR and XOR, as well as a variety of algebraic functions, including any addition , subtraction, multiplication, division. Some 5066 ALUs are designed for scalar operations and some for floating point. The data can be Big Endian (where the least significant byte is at the highest byte address) or Little Endian (where the least significant byte is at the lowest byte address) depending on the architecture. IBM's z / Architecture® is Big Endian. Signed fields can be sign and dimension, complement of 1 or complement of 2 depending on the architecture. A complement number of 2 is advantageous in that the ALU does not need to design a subtraction capability, since either a negative value or a positive value in the complement of 2 requires only an addition within the ALU. Numbers are commonly described in an abbreviated form, in which a 12-bit field defines an address of a 4,096-byte block and is commonly described as a 4-Kbyte block (Kilo-byte), for example.
[0122] Referring to Figure 15B, branch instruction information for executing a branch instruction is typically sent to a 5058 branch unit that generally employs a branch prediction algorithm, such as a 5082 branch history table for predict the outcome of the branch before other conditional operations are completed. The target of the current branch instruction will be searched and loaded and speculatively executed before the conditional operations are completed. When the conditional operations are completed, the speculatively executed branch instructions are completed or discarded based on the conditions of the conditional operation and the speculated result. A typical branching statement can test condition codes and branch to a target address if the condition codes meet the branching requirement of the branching statement, a target address can be calculated based on various numbers including those found in the registration fields or an immediate field of instruction, for example. The 5058 branch unit can employ an ALU 5074 having a plurality of 5075, 5076, 5077 input register circuits and a 5080 output register circuit. The 5058 branch unit can communicate with 5059 general registers, decode the shipping 5056 or other 5073 circuits, for example.
[0123] The execution of a group of instructions can be interrupted for a variety of reasons including a context switch initiated by an operating system, an exception or program error causing a context switch, an I / O interrupt signal causing a switching of context or multisegmented activity from a plurality of programs (in a multisegmented environment), for example. Preferably, a context switching action saves state information about a program currently running and then loads state information about another program being invoked. State information can be saved in hardware logs or in memory, for example. State information preferably comprises a program counter value pointing to a next instruction to be executed, condition codes, memory translation information and architecture record content. A context switching activity can be performed by hardware circuits, application programs, operating system programs or firmware code (microcode, pico-code or licensed internal code (LIC)) alone or in combination.
[0124] A processor accesses operands according to defined instruction methods. The statement can provide an immediate operand using the value of a portion of the statement, it can provide one or more record fields explicitly pointing to general purpose records or special purpose records (floating point records, for example). The instruction can use implicit records identified by an operation code field as operands. The instruction can use memory locations for operands. An operand's memory location can be provided by a record, an immediate field, or a combination of records and immediate field as exemplified by the z / Architecture® long scroll facility, where the instruction defines a base record, a record of index and an immediate field (displacement field) that are added together to provide the address of the operand in memory, for example. Location in this document typically implies a location in main memory (main storage) unless otherwise noted.
[0125] Referring to Figure 15C, a processor accesses storage using a 5060 loading / storage unit. The 5060 loading / storage unit can perform a loading operation by obtaining the address of the target operand in memory 5053 and by loading the operating in a 5059 register or other 5053 memory location, or it can perform a storage operation by obtaining the address of the target operand in memory 5053 and storing data obtained from a 5059 register or another 5053 memory location in the location of the target operand in memory 5053. The 5060 loading / storage unit can be speculative and can access memory in a sequence that is out of order with respect to the instruction sequence, however, the 5060 loading / storage unit must maintain the appearance for programs whose instructions were performed in order. A 5060 loading / storage unit can communicate with general 5059 registers, 5056 decoding / sending unit, 5053 memory / cache interface or other 5083 elements and comprises several register circuits, 5085 ALUs and 5090 control logic to calculate addresses storage and to provide sequencing to keep operations in order. Some operations may be out of order, but the loading / storage unit provides functionality to make out of order operations appear to the program as having been performed in order, as is well known in the art.
[0126] Preferably, addresses that an application program "views" are generally referred to as virtual addresses. Virtual addresses are often referred to as "logical addresses" and "effective addresses". These virtual addresses are virtual because they are redirected to the physical memory location by one of a variety of dynamic address translation (DAT) technologies including, but not limited to, simply prefixing a virtual address with a compensation value, translating the virtual address through one or more translation tables, the translation tables preferably comprising at least one segment table and one page table alone or in combination, preferably the segment table having an entry pointing to the page table. In z / Architecture®, a translation hierarchy is provided including a first region table, a second region table, a third region table, a segment table and an optional page table. The performance of address translation is generally improved using a translation buffer (TLB) which comprises mapping entries from a virtual address to an associated physical local memory. Entries are created when the DAT translates a virtual address using the translation tables. Subsequent use of the virtual address can then use the fast TLB entry instead of slow sequential translation table accesses. The TLB content can be managed by a variety of replacement algorithms including LRU (Least Recently Used).
[0127] In the event that the processor is a processor of a multiprocessor system, each processor has the responsibility of maintaining shared resources, such as I / O, cache memories, TLBs and memory, blocked for consistency. Typically, 'snoop' technologies will be used to maintain cache memory coherence. In a snoop environment, each line of cache memory can be marked as being in either a shared state, a unique state, an altered state, an invalid state, and the like to facilitate sharing.
[0128] 5054 I / O units (Figure 21) provide the processor with means of connecting to peripheral devices including tape, disk, printers, screens and networks, for example. I / O units are usually presented to the computer program by software units. In mainframes, such as IBM® System z®, channel adapters and open system adapters are mainframe I / O units that provide communication between the operating system and peripheral devices.
[0129] In addition, other types of computing environments can benefit from one or more aspects of the present invention. As an example, an environment may include an emulator (for example, software or other emulation mechanisms), in which a particular architecture (including, for example, instruction execution, architectural functions, such as address translation and architectural records ) or a subset of it is emulated (for example, on a native computer system having a processor and memory). In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, although a computer running the emulator may have a different architecture than the capabilities being emulated. As an example, in emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
[0130] In an emulation environment, a host computer includes, for example, memory to store instructions and data; an instruction search unit for searching and loading instructions from memory and, optionally, providing local temporary memory for the searched and loaded instruction; an instruction decoding unit for receiving the searched and loaded instructions and for determining the type of instructions that were searched and loaded; and an instruction execution unit for executing instructions. Execution may include loading data into a memory register; storing data back into memory from a record; or performing some kind of logical or arithmetic operation, as determined by the decoding unit. In one example, each unit is implemented in software. For example, the operations being performed by the units are implemented as one or more subroutines within emulator software.
[0131] More particularly, on a mainframe, architectural machine instructions are used by programmers, usually current "C" programmers, usually through a compiler application. These instructions stored on the storage medium can be executed natively on an IBM® z / Architecture® Server, or alternatively on machines running other architectures. They can be emulated on existing and future IBM® mainframe servers and other IBM® machines (for example, Power System servers and System x® servers). They can run on machines running Linux on a wide variety of machines using hardware manufactured by IBM®, Intel®, AMD ™ and others. In addition to running on that hardware under Z / Architecture®, Linux can be used and also machines that use emulation by Hercules (see eee.hercules-90.org) or ESI (Fundamental Software, Inc) (see www.funsoft.com) , where execution is usually in emulation mode. In emulation mode, the emulation software is run by a native processor to emulate the architecture of an emulated processor.
[0132] The native processor typically runs emulation software comprising firmware or a native operating system to perform emulation of the emulated processor. The emulation software is responsible for searching and loading and executing instructions for the emulated processor architecture. The emulation software maintains an emulated program counter to keep track of instruction boundaries. Emulation software can search and load one or more emulated machine instructions at once and convert one or more emulated machine instructions into a group of corresponding native machine instructions for execution by the native processor. These converted instructions can be cached, such that a faster conversion can be performed. Nevertheless, the emulation software must maintain the architectural rules of the emulated processor architecture, in order to ensure that the operating systems and applications written on the emulated processor operate correctly. In addition, the emulation software must provide features identified by the emulated processor architecture including, but not limited to, control records, general purpose records, floating point records, dynamic address translation function including segment tables and page tables , for example, interrupt mechanisms, context switching mechanisms, Time of Day (TOD) clocks and architectural interfaces for I / O subsystems, such that an operating system or application program designed to run on the emulated processor can be run on the native processor with the emulation software.
[0133] A specific instruction being emulated is decoded, and a subroutine is called to execute the function of the individual instruction. An emulation software function emulating an emulated processor function is implemented, for example, in a "C" unit or subroutine, or some other method of providing a unit for specific hardware as will be within the skill of those skilled in the art after understanding the description of the preferred embodiment. Various software and hardware emulation patents including, but not limited to, United States Patent No. 5,551,013, entitled "Multiprocessor for Hardware Emulation", by Beausoleil et al. ; and United States Patent No. 6,009,261, entitled "Preprocessing of Stored Target Routines for Emulating Incompatible Instructions on a Target Processor", by Scalzi et al; and United States Patent No. 5,574,873, entitled "Decoding Guest Instruction to Directly Access Emulation Routines that Emulate the Guest Instructions", by Davidian et al; and United States Patent No. 6,308,255, entitled "Symmetrical Multiprocessing Bus and Chipset Used for Coprocessor Support Allowing Non-Native Code to Run in a System", by Gorishek et al; and United States Patent No. 6,463,582, entitled "Dynamic Optimizing Object Code Translator for Architecture Emulation and Dynamic Optimizing Object Code Translation Method", by Lethin et al; and United States Patent Letter No. 5,790,825, entitled "Method for Emulating Guest Instructions on a Host Computer Through Dynamic Recompilation of Host Instructions" by Eric Traut, and many others, illustrate a variety of known ways of emulating an architectural instruction format for a different machine to a target machine available to those skilled in the art.
[0134] In Figure 16, an example of a 5092 emulated host computer system is provided, which emulates a host architecture system 5000 'of a host architecture. In the 5092 emulated host computer system, the 5091 host processor (CPU) is an emulated host processor (or virtual host processor) and comprises a 5093 emulation processor having a native instruction set architecture different from the 5091 processor of the host computer 5000 ' . The 5092 emulated host computer system has 5094 memory accessible to the 5093 emulation processor. In the embodiment example, the 5094 memory is divided into a portion of the 5096 host computer memory and a portion of the 5097 emulation routines. The host computer memory 5096 is available to programs on the 5092 emulated host computer according to the host computer architecture. The 5093 emulation processor executes native instructions from an architecture instruction set of a different architecture than the 5091 emulated processor, the native instructions obtained from the memory of 5097 emulation routines, and can access a host instruction for executing a program in memory of 5096 host computer employing one or more instruction (s) obtained in a sequence & access / decoding routine that can decode the accessed host instruction (s) to determine a native instruction execution routine to emulate the function of the host instruction accessed. Other facilities that are defined for the architecture of the host computer system 5000 'can be emulated by architectural facility routines, including such facilities as general purpose records, control records, dynamic address translation and I / O subsystem support. and processor cache memory, for example. Emulation routines can also take advantage of functions available on the 5093 emulation processor (such as general registration and dynamic translation of virtual addresses) to improve the performance of emulation routines. Special download mechanisms and hardware can also be provided to assist the 5093 processor in emulating the host computer's 5000 'function.
[0135] The terminology used here is only intended to describe particular embodiments and is not intended to limit the invention. As used herein, the singular forms "one", "one", "o" and "a" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises" and / or "comprising", when used in this invention, specify the presence of declared characteristics, integers, steps, operations, elements and / or components, but do not prevent the presence or addition of a or more features, integers, steps, operations, elements, components and / or groups thereof.
[0136] The structures, materials, actions and corresponding equivalents of all means or stages plus the function elements in the claims below, if any, are intended to include any structure, material or action to perform the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the disclosed form. Many modifications and variations will be evident to those skilled in the art without departing from the scope of the invention. The embodiment has been chosen and described in order to better explain the principles of the invention and the practical application, and to allow others skilled in the art to understand the invention for various embodiments with various modifications that are suitable for the particular intended use.

权利要求:
Claims (7)
[0001]
1. A method for translating addresses in a computing environment comprising: obtaining an address from an adapter (110) to be translated into a memory address directly usable in accessing the memory of the computing environment system, the address comprising a plurality of bits, the plurality of bits comprising a first portion of bits and a second portion of bits; receive an address range value that indicates a range of allowed addresses, where the range is defined by a base address (214) and a limit (216) located in a device table entry (210) associated with the adapter (110 ), the device table entry (210) located by a requester identifier located in a request issued by the adapter (110); validating the address obtained from the adapter (110) using at least the first bit portion and the received address range; and converting the address obtained from the adapter (110) to the memory address directly usable in the accessible system memory of the computing environment, the method characterized by the fact that the conversion ignores the first portion of bits and uses the second portion of bits for information about the address of one or more levels of address translation tables to perform the conversion.
[0002]
2. Method according to claim 1, characterized in that the first portion of bits comprises high order bits of the address and the second portion of bits comprises lower order bits of the address, the low order bits determined on the basis of in a dimension of an allocated address space that includes the memory address.
[0003]
3. Method according to claim 1, characterized by the fact that a number of levels of address translation tables are based on at least one of a size of an assigned address space, which includes the memory address, the size of one or more address translation tables to be used in the conversion, and a size of the memory unit accessed by the memory address.
[0004]
4. Method, according to claim 1, characterized by the fact that the conversion comprises selecting an address translation table to be used to convert the address, the selection using a pointer on a device table entry (210) used in the conversion.
[0005]
5. Method according to claim 4, characterized in that the method further comprises the location of the device table entry (210), the location using at least one of an adapter requesting identifier (110) that issues a request that includes the address to be translated, or a portion of the address.
[0006]
6. Method, according to claim 4, characterized by the fact that the method further comprises the determination of a format of the selected address translation table, the determination using a format field of the device table entry (210).
[0007]
7. Computer system characterized by the fact that it comprises the means adapted to carry out all stages of the method, as defined in any one of claims 1 to 6.

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同族专利:

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公开号 | 公开日

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AU2010355813A1|2012-12-20|

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US20130067194A1|2013-03-14|

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CN102906719B|2015-07-08|

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HRP20130820T1|2013-10-11|

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CA2800636C|2018-03-13|

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RU2012147515A|2014-05-20|

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AU2010355813B2|2014-05-22|

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CN102906719A|2013-01-30|

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US9626298B2|2017-04-18|

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ZA201209649B|2014-05-28|

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SG186098A1|2013-01-30|

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CA2800636A1|2011-12-29|

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WO2011160722A1|2011-12-29|

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JP2013537658A|2013-10-03|

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HK1180793A1|2013-10-25|

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US8631222B2|2014-01-14|

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US20140129796A1|2014-05-08|

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KR101455544B1|2014-10-27|

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KR20130048762A|2013-05-10|

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DK2430555T3|2013-09-30|

---

JP5636097B2|2014-12-03|

---

EP2430555A1|2012-03-21|

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EP2430555B1|2013-08-28|

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US8635430B2|2014-01-21|

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MX2012014859A|2013-02-01|

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BR112012033815A2|2018-04-17|

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SI2430555T1|2013-10-30|

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US20110320758A1|2011-12-29|

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RU2547705C2|2015-04-10|

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ES2428822T3|2013-11-11|

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PT2430555E|2013-10-03|

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PL2430555T3|2013-11-29|

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法律状态:
2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

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2019-08-13| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2020-07-14| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2020-11-03| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 08/11/2010, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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US12/821,170|2010-06-23|

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US12/821,170|US8635430B2|2010-06-23|2010-06-23|Translation of input/output addresses to memory addresses|

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PCT/EP2010/067043|WO2011160722A1|2010-06-23|2010-11-08|Translation of input/output addresses to memory addresses|

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